Integrated circuit semiconductor devices or modules since their first fabrication and use in the 1960's have truly revolutionized our world. Commonly referred to as integrated circuit chips or computer chips, their development and sophistication has accelerated steadily over the years. The first chips had only a few circuit elements; nowadays, chips or modules commonly have tens of thousands of circuit elements on them and can perform a wide variety of sophisticated functions.
One aspect of this increasing sophistication involves the addition of circuitry which allows the module to enter various special operational modes on receipt of the appropriate sequence of signals. Test modes implemented by circuitry built into the module constitute one broad category of operational modes. The signals used to put the module into a special operational mode generally consist of the standard signals the module normally uses during most functions, with the normal sequence of signals altered. This avoids the need for special dedicated pins or connections. However, glitches, such as power interruptions, or failure to maintain the proper sequence of signals can cause the module to exit the special operational mode with no indication that it no longer remains in the desired operational mode.
In some instances, the electronics industry has standards, promulgated by various professional organizations, to follow in fabricating modules with standard operational modes. The Solid State Products Engineering Counsel, JEDEC, on or about Apr. 22, 1987 approved LTRB JC-42.3-86-95A "Optional Special Modes For Address Multiplexed DRAM." This JEDEC publication is incorporated herein by reference. The standards set forth in the JEDEC publication define a scheme for: a.) controlling various special modes for address multiplexed DRAMS; b.) the logic required to enter, control and exit from the special modes; and c.) the basic special test modes plus other special test modes and operational modes. One problem not resolved by the standards is, how to monitor the module to determine that the module is in a special operating mode and to assure that the module remains in the special operating mode for a desired period of time and does not prematurely exit from the special operating mode.
An example will serve to illustrate the problem. One type of test mode circuitry built into a multiplexed DRAM, when activated, increases the voltage in the memory cells above the normal voltage levels the cells experience during normal operation. Burn-in tests conducted shortly after manufacture of the memory module would use this feature. A burn-in test consists of: a.) elevating the voltage in the memory cells of the DRAM to a potential of at least 1 or 2 volts above the normal voltage the DRAM would experience during normal operation; b.) placing the DRAM in an ambient temperature higher than it would normally experience and c.) maintaining these conditions for a specified period of time. Special test ovens with appropriate equipment to put the chips or modules into the necessary test mode can conduct mass tests on large numbers of modules at one time.
Burn-in tests stress the oxide or dielectric connections of a DRAM. The oxide or dielectric connections of a DRAM are located at the gate of the transistors, at the connection between the storage capacitor and the transistor, between the transistor and the bit lines, as well as at other locations throughout the DRAM. Burn-in when properly done, helps eliminate DRAMS with defective oxide or dielectric connections. These defective connections can be a major source of failure for DRAMS during normal operation. Consequently, when properly conducted, burn-in tests increase the reliability of the end product.
The JEDEC standards provide for the initiation of a test mode on a DRAM through a reversal of the sequence of the row address signal (RAS), column address signal (CAS) and read/write signal (W), coupled with decoding of a portion of the row address. However, there is no provision for monitoring module operation in a test mode. Further, as known in the art, the DRAM can exit from the test mode prematurely for several reasons including a momentary power glitch or an improper refresh cycle, both of which would not affect the normal operation of the DRAM and are not otherwise noticeable. If such a failure occurs during a burn-in test and the DRAM falls out of its test mode, given the current state of the technology, the test equipment does not sense this, nor does the tester receive any warning thereof. When the test fails, the memory devices tested experience a higher than usual failure rate during normal operations.
One approach to solve this problem would be to add an extra pin or connection to the DRAM solely for the monitoring of special operational modes. However, this uses a valuable connection or pin which could otherwise be used for other purposes. The challenge then is to provide a method and apparatus for monitoring test and other special operational modes and for signalling a loss or change in such an operational mode, without the necessity of adding a special or dedicated pin or connection to the module.